Semiconductor chips are connected to external circuitry through electrical contacts on a face surface of the chip. The contacts on the chip typically are disposed in the regular patterns such as a grid substantially covering the front surface of the chip, commonly referred to as an "area array" or in elongated rows extending parallel to and adjacent each edge of the chip face surface. Each contact on the chip must be connected to external circuitry, such as the circuitry of a supporting substrate or circuit panel. Various processes for making these interconnections use prefabricated arrays of leads or discrete wires. For example, in a ball or stitch bonding process using a wirebonder, the chip is physically mounted on the substrate. A fine wire is fed through a bonding tool. The tool is brought into engagement with the contact on the chip so as to bond the wire to the contact. The tool is then moved to a connection point of the circuit on the substrate, so that a small piece of wire is dispensed and formed into a lead, and connected to the substrate. This process is repeated for every contact on the chip.
In the so-called tape automated bonding or "TAB" process, a dielectric supporting tape, such as a thin foil of polyimide is provided with an aperture slightly larger than the chip. An array of metallic leads is provided on one surface of the dielectric film. These leads extend inwardly from around the aperture towards the edges of the aperture. Each lead has an innermost end projecting inwardly, beyond the edge of the aperture. The innermost ends of the leads are arranged side by side at spacing corresponding to the spacing of the contacts on the chip. The dielectric film is juxtaposed with the chip so that the aperture is aligned with the chip and so that the innermost ends of the leads will extend over the front or contact bearing surface on the chip. The innermost ends of the leads are then bonded to the contacts of the chip, as by ultrasonic or thermocompression bonding. The outer ends of the leads are connected to external circuitry.
In a so-called "beam lead" process, the chip is provided with individual leads extending from contacts on the front surface of the chip outwardly beyond the edges of the chip. The chip is positioned on a substrate with the outermost ends of the individual leads protruding over contacts on the substrate. The leads are then engaged with the contacts and bonded thereto so as to connect the contacts on the chip with contacts on the substrate.
The rapid evolution of the semiconductor art in recent years has created a continued demand for progressively greater numbers of contacts and leads in a given amount of space. An individual chip may require hundreds or even thousands of contacts, all within the area of the chip face surface. For example, a complex semiconductor chip in current practice may have a row of contacts spaced apart from one another at center-to-center distances of 0.1 mm or less and, in some cases, 0.05 mm or less. These distances are expected to decrease progressively with continued progress in the art of semiconductor fabrication.
With such closely-spaced contacts, the leads connected to the chip contacts, such as the wires used in wirebonding leads in the tab process and beam leads must be extremely fine structures, typically having a smaller bonded surface than the contacts onto which they are bonded so that the adjacent lead do not electrically short. Such fine structures are susceptible to damage and deformation. With closely spaced contacts, even minor deviations of a lead from its normal position will result in misalignment of the leads and contacts. Thus, a given lead may be out of alignment with the proper contact on the chip or substrate, or else it may be erroneously aligned with an adjacent contact. Either condition will yield a defective chip assembly. Errors of this nature materially reduce the yield of good devices and introduce defects into the product stream. These problems are particularly acute with those chips having relatively fine contact spacing and small distances between adjacent contacts.
Commonly assigned U.S. patent application Ser. No. 07/919,772, filed Jul. 24, 1992 (the "772 application") and issued U.S. Pat. No. 5,489,749 which is a divisional thereof, the disclosures of which are incorporated by reference herein, describes an improved system for connecting semiconductor chips to external circuitry. Certain embodiments of the invention set forth in the '772 application utilize a connection component having a support structure and electrically conductive leads. Each lead has a connection section extending across a gap in the support structure. The connection sections of the leads are flexible. Preferably, one end of each lead is detachably secured to the support structure, whereas the other end is permanently secured to the support structure and connected to a terminal mounted on the support structure. The connection component is positioned on a part of a semiconductor chip assembly, such as the chip itself, so that the leads overlie contacts on the part or chip. The connection sections of the leads are bonded to the contacts on the chip by engaging each connection section with a tool, forcing the tool downwardly to break the detachable end of the lead from the support structure and bring the connection section into engagement with a contact on the chip. The tool is used to apply pressure and/or ultrasonic vibrations to the lead, thereby forming a bond between the lead and the contact of the chip. This process is repeated for each lead, until all the leads have been bonded to the contacts on the chip. After the connection component has been electrically connected to the contacts of the chip, the terminals of the connections component can be used to connect the chip to other, external circuitry as, for example, by bonding the terminals of the connection component to an external substrate such as a circuit panel.
In the preferred arrangements disclosed in the '772 application, the bonding tool is arranged to capture and align the lead. Thus, the bonding tool may be a blade-like device with an elongated bottom edge and with a groove extending lengthwise along such bottom edge for engaging leads to be bonded. The groove may have a central plane and surfaces sloping upwardly from the sides of the groove towards the central plane. When the tool is roughly aligned with a lead, so that the lengthwise axis of the bottom edge and groove are generally parallel to the lengthwise axis of the connection section of the lead, the groove will engage the lead and guide it into precise alignment with the tool. Thus, the tool can be aligned in sequence with each contact, and engaged with a lead. Even if the lead is slightly out of alignment with the contact and tool at the beginning of the operation, the tool will bring the lead into precise alignment with the tool and hence with the contact during the downward motion of the tool. Thus, minor dimensional variations in the connection component do not impede the process, even where the contacts are provided at very small spacing.
The preferred embodiments described in the '772 application are highly advantageous, but still further improvement would be desirable. In many cases, the connection sections of different leads extend in different, mutually orthogonal directions. For example, many common chips are generally rectangular and have contacts disposed in rows extending along the edges of the chip. The rows of contacts on adjacent edges extend in mutually orthogonal directions. The connection sections of the leads associated with each row of contacts on the chip must be arranged side by side, so that the connection sections of the leads extend orthogonally to the length of the row. Thus, where the rows of contacts extend in mutually orthogonal directions along different edges of the chip, the connection sections of the leads likewise extend in mutually orthogonal directions. Typically, the tool is positioned so that the lengthwise axis of the bottom edge extends parallel to the connection sections in one row, and the tool is then advanced stepwise down the row, bonding each of the leads in the row seriatim. When the row is completed, the chip and support structure must be rotated 90.degree. relative to the tool so as to properly align the tool for engagement with the connection sections of the next row.
The rotation step consumes appreciable time in production and requires that the apparatus be equipped with a precise, rotatable stage or mounting. Moreover, the rotation step can introduce additional misalignments between the connection sections and the tool.
Commonly assigned U.S. Pat. No. 5,390,844, incorporated herein by reference, deals effectively with this problem. One embodiment of that patent provides a bonding tool for bonding leads to contacts on semiconductor chips wherein the lower end of the tool defines guide surfaces for engaging elongated leads disposed beneath the lower end of the tool upon downward movement of the tool from above the leads. The guide surfaces are adapted to engage a lead extending in either of two mutually orthogonal directions and to center the engaged lead beneath the bonding region of the lower end so that the lead can be engaged and bonded by the tool. With either orientation of the lead, the tool will capture and align the lead, and bring the lead into position for bonding. Thus, a tool in accordance with this aspect of the present invention can be used in procedures generally similar to those discussed above with reference to the '772 application and in bonding TAB-like cantilevered leads. However, where the leads on the connection component extend in two mutually orthogonal directions, there is no need to rotate the connection component and chip relative to the tool during the process. Where the contacts are arranged in rows, the tool can simply be advanced along one row, then advanced along another row, until the process is complete. Other embodiments and improvements are further disclosed in the '844 patent.
Proper bonding of the leads to respective chip contacts is also important. Typically, the leads are bonded to the chip contacts by the bonding tool using heat, force, ultrasonic energy, or a combination of two or more thereof, for a given time period. If an incorrect ratio of force, heat and/or ultrasonic energy is used, the bond between the leads and the contacts may be too weak to undergo the thermal cycling stress during operation of the chip (heating and cooling cycles during operation). The bonding tool may create areas of the lead which are prone to early fatigue during thermal cycling because of excessive non-uniform deformations in the bonding region typically causing early breaks in the lead at the point the lead bends up from the chip surface (commonly referred to as a "heel break"). Further, obtaining good intermetallic bonds which are substantially uniform across the surface of the bond between the lead and contact surfaces is critical to a well performing lead bond. Uneven intermetallic growth can cause embrittlement of the lead in and around the bond area thereby causing early fatigue of the lead during thermal cycling. Intermetallic diffusion will typically only take place at the bonded sites of the lead and the contact thereby causing sites of gross intermetallic formation which may cause an unreliable bond. Further, impurities in the bond lead (such as co-deposited plated lead impurities or other surface impurities) tend to migrate to the unevenly bonded intermetallic sites during the high temperatures used in chip packaging thus weakening the bond. Both of these problems may worsen the creation of a phenomenon called Kirkendahl Voiding (voids created at the boundary of two metals having different interdiffusion coefficients). This voiding along the boundary of the two metals (lead/contact) generally causes intermetallic degradation, brittleness of the lead itself and weakening of the bond making the lead/bond susceptible to failure during thermal cycling.
As chip packages are made smaller and smaller, the lead dimensions will also be reduced compounding this problem by making it more difficult to reliably bond the leads to their respective chip contacts using conventional bonding tools. FIG. 1A shows a fragmentary side view of a single point bonding tool. FIGS. 1B-1G show the bonding surface view (view A--A from FIG. 1A) of various prior art lead bonding tool designs which have the tendency to cause the aforementioned problems especially as the lead dimensions continue to get smaller. A drawing of a typical bonder tool is depicted in FIG. 1H. The tool in FIG. 1H has a cross groove formed into the bonding surface region of the tool. Each bonding surface shown in FIGS. 1B-H is designed with the intent to maximize the coupling of the energy from the tool to form a good bond between the lead and a contact. The tools are typically made of very hard materials which are electrically conductive as they are manufactured using electrodischarge machining to obtain the ultra-fine features. The cross grooves in the tool shown in FIG. 1H are about 10 micrometers wide, as limited by the aforementioned electroforming process. The various groove designs on the bonding surfaces of the bonding tools discussed above have the tendency to cut too deeply or make too deep of an impression in finely dimensioned leads during the bonding of the leads to respective chip contacts potentially causing weak portions of the leads which are more likely to break during thermal cycling of the device and more likely to cause non-uniform bonding conditions, as described earlier. Also, potential problems maybe cause by "cratering" the surface of the chip contacts during bonding by placing too much concentrated force on the fine leads.
Despite the substantial time and effort devoted heretofore to the problems associated with providing bonding tools, there are still unmet needs for improvements in such semiconductor chip package structures and methods.